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? semiconductor components industries, llc, 2015 march, 2015 ? rev. 1 1 publication order number: nlsx4401/d nlsx4401 1-bit 20 mb/s dual-supply level translator the nlsx4401 is a 1?bit configurable dual?supply bidirectional auto sensing translator that does not require a directional control pin. the i/o v cc and i/o v l ports are designed to track two different power supply rails, v cc and v l respectively. both the v cc and v l supply rails are configurable from 1.5 v to 5.5 v. this allows voltage logic signals on the v l side to be translated into lower, higher or equal value voltage logic signals on the v cc side, and vice?versa. the nlsx4401 translator has integrated 10 k pull?up resistors on the i/o lines. the integrated pull?up resistors are used to pull up the i/o lines to either v l or v cc . the nlsx4401 is an excellent match for open?drain applications such as the i 2 c communication bus. features ? v l can be less than, greater than or equal to v cc ? wide v cc operating range: 1.5 v to 5.5 v wide v l operating range: 1.5 v to 5.5 v ? high speed with 24 mb/s guaranteed date rate ? low bit?to?bit skew ? enable input and i/o pins are overvoltage tolerant (ovt) to 5.5 v ? non?preferential powerup sequencing ? power?o ff protection ? integrated 10 k pull?up resistors ? small space saving package: 1.45 mm x 1.0 mm udfn6 package ? these devices are pb?free and are rohs compliant typical applications ? i 2 c, smbus, pmbus ? low voltage asic level translation ? mobile phones, pdas, cameras important information ? esd protection for all pins ? human body model (hbm) > 5000 v marking diagrams http://onsemi.com udfn6 1.45 x 1.0 case 517aq device package shipping ? ordering information NLSX4401MU1TCG udfn6 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd801 1/d. y = specific device code (rotated 270 clockwise) m = date code v l v cc gnd en i/o v l i/o v cc logic diagram 1 m y
nlsx4401 http://onsemi.com 2 figure 1. block diagram (1 i/o line) figure 2. pinout diagram udfn6 (top through v iew) 1 2 3 6 5 4 v l i/o v l gnd v cc i/o v cc en pin assignment pins description v cc v cc supply voltage v l v l supply voltage gnd ground en output enable, referenced to v l i/o v cc i/o port, referenced to v cc i/o v l i/o port, referenced to v l function table en operating mode l hi?z h i/o buses connected
nlsx4401 http://onsemi.com 3 maximum ratings symbol parameter value condition unit v cc high?side dc supply v oltage ?0.5 to +7.0 v v l high?side dc supply v oltage ?0.5 to +7.0 v i/o v cc v cc ?referenced dc input/output v oltage ?0.5 to +7.0 v i/o v l v l ?referenced dc input/output v oltage ?0.5 to +7.0 v v en enable control pin dc input v oltage ?0.5 to +7.0 v i i/o_sc short?circuit duration (i/o v l and i/o v cc to gnd) 50 continuous ma i i/ok input/output clamping current (i/o v l and i/o v cc ) ?50 v i/o < 0 ma t stg storage t emperature ?65 to +150 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. recommended opera ting conditions symbol parameter min max unit v cc high?side positive dc supply v oltage 1.5 5.5 v v l high?side positive dc supply v oltage 1.5 5.5 v v en enable control pin v oltage gnd 5.5 v v io_vcc i/o pin voltage (side referred to v cc ) gnd 5.5 v v io_vl i/o pin voltage (side referred to v l ) gnd 5.5 v t/ v input transition rise and fall rate a? or b?ports, push?pull driving control input 10 10 ns/v t a operating temperature range ?55 +125 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond th e recommended operating ranges limits may affect device reliability.
nlsx4401 http://onsemi.com 4 dc electrical characteristics (v l = 1.5 v to 5.5 v and v cc = 1.5 v to 5.5 v, unless otherwise specified) (note 1) symbo l parameter test conditions (note 2) ?55 c to +125 c uni t min typ max v ihc i/o v cc input high voltage v cc ? 0.4 ? ? v v ilc i/o v cc input low v oltage ? ? 0.15 v v ihl i/o vl input high v oltage v l ? 0.4 ? ? v v ill i/o vl input low v oltage ? ? 0.15 v v ih control pin input high v oltage 0.65 * v l ? ? v v il control pin input low v oltage ? ? 0.35 * v l v v ohc i/o v cc output high voltage i/o v cc source current = 20 a 2/3 * v cc ? ? v v olc i/o v cc output low v oltage i/o v cc sink current = 1 ma ? ? 0.4 v v ohl i/o v l output high voltage i/o v l source current = 20 a 2/3 * v l ? ? v v oll i/o v l output low v oltage i/o v l sink current = 1 ma ? ? 0.4 v i qvcc v cc supply current supply current i/o v cc and i/o v l unconnected, v en = v l v l = 5.5 v, v cc = 0 v v l = 0 v, v cc = 5.5 v ? ? ? 0.5 ? ? 2.0 1.0 ? 1.0 a i qvl v l supply current supply current i/o v cc and i/o v l unconnected, v en = v l v l = 5.5 v, v cc = 0 v v l = 0 v, v cc = 5.5 v ? ? ? 0.3 ? ? 1.5 ? 1.0 1.0 a i ts?vcc v cc tristate output mode i/o v cc and i/o v l unconnected, v en = gnd ? 0.1 1.0 a i ts?vl v l tristate output mode supply cur- rent i/o v cc and i/o v l unconnected, v en = gnd ? 0.1 1.0 a i i enable pin input leakage current ? ? 1.0 a i off i/o power - off leakage current i/o v cc port, v cc = 0 v, v l = 0 to 5.5 v ? ? 1.0 a i/o vl port, vcc = 0 to 5.5 v, v l = 0 v ? ? 1.0 i oz i/o tristate output mode leakage current ? 0.1 1.0 a r pu pull?up resistors i/o v l and v c ? 10 ? k product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. typical values are for v l = +1.8 v, v cc = +3.3 v and t a = +25 c. 2. all units are production tested at t a = +25 c. limits over the operating temperature range are guaranteed by design.
nlsx4401 http://onsemi.com 5 timing characteristics ? rail?to?rail driving configura tions (i/o test circuit of figures 3 and 4, c load = 15 pf, driver output impedance 50 , r load = 1 m ) symbol parameter test conditions ?40 c to +85 c (notes 3 & 4) unit min typ max v l = 1.5 v, v cc = 1.5 v t rvcc i/o v cc rise time 9 32 ns t fvcc i/o v cc fall time 11 20 ns t rvl i/o v l rise time 20 30 ns t fvl i/o v l fall time 10 13 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 7 16 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 12 15 ns t en enable time 50 ns t dis disable time 300 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 15 mbps v l = 1.5 v, v cc = 5.5 v t rvcc i/o v cc rise time 9 12 ns t fvcc i/o v cc fall time 17 30 ns t rvl i/o v l rise time 2 4 ns t fvl i/o v l fall time 3 7 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 14 24 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 3 5 ns t en enable time 40 ns t dis disable time 250 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 20 mbps v l = 1.8 v, v cc = 2.8 v t rvcc i/o v cc rise time 11 18 ns t fvcc i/o v cc fall time 10 15 ns t rvl i/o v l rise time 12 15 ns t fvl i/o v l fall time 5 8 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 7 10 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 5 9 ns t en enable time 50 ns t dis disable time 300 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 20 mbps v l = 2.5 v, v cc = 3.6 v t rvcc i/o v cc rise time 8 12 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. typical values are for the specified v l and v cc at t a = +25 c. all units are production tested at t a = +25 c. 4. limits over the operating temperature range are guaranteed by design. 5. skew is the variation of propagation delay between output signals and applies only to output signals on the same port (i/o_vln or i/o_v ccn) and switching with the same polarity (low?to?high or high?to?low). skew is defined by applying a single input to the two input channels and measuring the difference in propagation delays between the output channels.
nlsx4401 http://onsemi.com 6 timing characteristics ? rail?to?rail driving configura tions (continued) (i/o test circuit of figures 3 and 4, c load = 15 pf, driver output impedance 50 , r load = 1 m ) symbol unit ?40 c to +85 c (notes 3 & 4) test conditions parameter symbol unit max typ min test conditions parameter v l = 2.5 v, v cc = 3.6 v t fvcc i/o v cc fall time 8 12 ns t rvl i/o v l rise time 7 10 ns t fvl i/o v l fall time 5 7 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 7 10 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 5 8 ns t en enable time 40 ns t dis disable time 225 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 24 mbps v l = 2.8 v, v cc = 1.8 v t rvcc i/o v cc rise time 13 20 ns t fvcc i/o v cc fall time 7 10 ns t rvl i/o v l rise time 8 13 ns t fvl i/o v l fall time 9 15 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 6 9 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 7 12 ns t en enable time 60 ns t dis disable time 250 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 24 mbps v l = 3.6 v, v cc = 2.5 v t rvcc i/o v cc rise time 9 12 ns t fvcc i/o v cc fall time 6 9 ns t rvl i/o v l rise time 6 12 ns t fvl i/o v l fall time 7 12 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 5 7 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 6 9 ns t en enable time 50 ns t dis disable time 250 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 24 mbps v l = 5.5 v, v cc = 1.5 v t rvcc i/o v cc rise time 13 20 ns t fvcc i/o v cc fall time 6 9 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. typical values are for the specified v l and v cc at t a = +25 c. all units are production tested at t a = +25 c. 4. limits over the operating temperature range are guaranteed by design. 5. skew is the variation of propagation delay between output signals and applies only to output signals on the same port (i/o_vln or i/o_v ccn) and switching with the same polarity (low?to?high or high?to?low). skew is defined by applying a single input to the two input channels and measuring the difference in propagation delays between the output channels.
nlsx4401 http://onsemi.com 7 timing characteristics ? rail?to?rail driving configura tions (continued) (i/o test circuit of figures 3 and 4, c load = 15 pf, driver output impedance 50 , r load = 1 m ) symbol unit ?40 c to +85 c (notes 3 & 4) test conditions parameter symbol unit max typ min test conditions parameter v l = 5.5 v, v cc = 1.5 v t rvl i/o v l rise time 8 10 ns t fvl i/o v l fall time 20 27 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 5 8 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 14 24 ns t en enable time ns t dis disable time ns t ppskew part?to?part skew 2 ns mdr maximum data rate 20 mbps v l = 5.5 v, v cc = 5.5 v t rvcc i/o v cc rise time 5 7 ns t fvcc i/o v cc fall time 6 8 ns t rvl i/o v l rise time 5 7 ns t fvl i/o v l fall time 4 7 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 4 6 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 4 6 ns t en enable time 30 ns t dis disable time 225 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 24 mbps product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 3. typical values are for the specified v l and v cc at t a = +25 c. all units are production tested at t a = +25 c. 4. limits over the operating temperature range are guaranteed by design. 5. skew is the variation of propagation delay between output signals and applies only to output signals on the same port (i/o_vln or i/o_v ccn) and switching with the same polarity (low?to?high or high?to?low). skew is defined by applying a single input to the two input channels and measuring the difference in propagation delays between the output channels. timing characteristics ? open drain driving configurations (i/o test circuit of figures 5 and 6, c load = 15 pf, driver output impedance 50 , r load = 1 m ) symbol parameter test conditions ?40 c to +85 c (notes 6 & 7) unit min typ max v l = 1.5 v, v cc = 1.5 v t rvcc i/o v cc rise time 55 70 ns t fvcc i/o v cc fall time 7 14 ns t rvl i/o v l rise time 50 65 ns t fvl i/o v l fall time 7 12 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. typical values are for the specified v l and v cc at t a = +25 c. all units are production tested at t a = +25 c. 7. limits over the operating temperature range are guaranteed by design. 8. skew is the variation of propagation delay between output signals and applies only to output signals on the same port (i/o_vln or i/o_v ccn) and switching with the same polarity (low?to?high or high?to?low). skew is defined by applying a single input to the two input channels and measuring the difference in propagation delays between the output channels.
nlsx4401 http://onsemi.com 8 timing characteristics ? open drain driving configurations (continued) (i/o test circuit of figures 5 and 6, c load = 15 pf, driver output impedance 50 , r load = 1 m ) symbol unit ?40 c to +85 c (notes 6 & 7) test conditions parameter symbol unit max typ min test conditions parameter v l = 1.5 v, v cc = 1.5 v t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 20 34 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 19 34 ns t en enable time 100 ns t dis disable time 300 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 3 mbps v l = 1.5 v, v cc = 5.5 v t rvcc i/o v cc rise time 22 34 ns t fvcc i/o v cc fall time 20 27 ns t rvl i/o v l rise time 43 55 ns t fvl i/o v l fall time 6 12 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 13 26 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 19 24 ns t en enable time 80 ns t dis disable time 250 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 3 mbps v l = 1.8 v, v cc = 3.3 v t rvcc i/o v cc rise time 34 40 ns t fvcc i/o v cc fall time 1 15 ns t rvl i/o v l rise time 40 48 ns t fvl i/o v l fall time 1 2 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 9 15 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 6 11 ns t en enable time 70 ns t dis disable time 300 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 7 mbps v l = 5.5 v, v cc = 1.5 v t rvcc i/o v cc rise time 44 52 ns t fvcc i/o v cc fall time 1 2 ns t rvl i/o v l rise time 7 30 ns t fvl i/o v l fall time 17 23 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 10 17 ns product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. typical values are for the specified v l and v cc at t a = +25 c. all units are production tested at t a = +25 c. 7. limits over the operating temperature range are guaranteed by design. 8. skew is the variation of propagation delay between output signals and applies only to output signals on the same port (i/o_vln or i/o_v ccn) and switching with the same polarity (low?to?high or high?to?low). skew is defined by applying a single input to the two input channels and measuring the difference in propagation delays between the output channels.
nlsx4401 http://onsemi.com 9 timing characteristics ? open drain driving configurations (continued) (i/o test circuit of figures 5 and 6, c load = 15 pf, driver output impedance 50 , r load = 1 m ) symbol unit ?40 c to +85 c (notes 6 & 7) test conditions parameter symbol unit max typ min test conditions parameter v l = 5.5 v, v cc = 1.5 v t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 12 24 ns t en enable time 100 ns t dis disable time 300 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 3 mbps v l = 5.5 v, v cc = 5.5 v t rvcc i/o v cc rise time 42 50 ns t fvcc i/o v cc fall time 2 3 ns t rvl i/o v l rise time 44 48 ns t fvl i/o v l fall time 2 3 ns t pdvl?vcc propagation delay (driving i/o v l , v l to v cc ) 4 6 ns t pdvcc?vl propagation delay (driving i/o v cc , v cc to v l ) 6 9 ns t en enable time 60 ns t dis disable time 225 ns t ppskew part?to?part skew 2 ns mdr maximum data rate 7 mbps product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 6. typical values are for the specified v l and v cc at t a = +25 c. all units are production tested at t a = +25 c. 7. limits over the operating temperature range are guaranteed by design. 8. skew is the variation of propagation delay between output signals and applies only to output signals on the same port (i/o_vln or i/o_v ccn) and switching with the same polarity (low?to?high or high?to?low). skew is defined by applying a single input to the two input channels and measuring the difference in propagation delays between the output channels.
nlsx4401 http://onsemi.com 10 test setup nlsx4401 en i/o v l v l v cc c load t rise/fall 3 ns i/o v l i/o v cc t pd_vl?vcc 90% 50% 10% 90% 50% 10% t pd_vl?vcc t f?vcc t r?vcc figure 3. rail?to?rail driving i/o v l i/o v cc nlsx4401 en i/o v l v l v cc c load source t rise/fall 3 ns i/o v cc i/o v l t pd_vcc?vl 90% 50% 10% 90% 50% 10% t pd_vcc?vl t f?vl t r?vl i/o v cc source figure 4. rail?to?rail driving i/o v cc nlsx4401 en i/o v l v l v cc figure 5. open?drain driving i/o v l i/o v cc nlsx4401 en v l v cc i/o v cc figure 6. open?drain driving i/o v cc figure 7. definition of timing specification parameters c load v cc c load r load r load r load r load
nlsx4401 http://onsemi.com 11 open pulse generator r t dut v cc r l r 1 c l 2xv cc test switch t pzh , t phz open t pzl , t plz 2 x v cc c l = 15 pf or equivalent (includes jig and probe capacitance) r l = r 1 = 50 k or equivalent r t = z out of pulse generator (typically 50 ) figure 8. test circuit for enable/disable time measurement v cc gnd t f t r 10% 50% 90% 10% 50% 90% t r t plh t phl t f 50% 50% 90% 10% t pzl t plz t pzh t phz gnd high impedance v ol v oh high impedance figure 9. timing definitions for propagation delays and enable/disable measurement en input 50% v l output output output
nlsx4401 http://onsemi.com 12 applications information level translator architecture the nlsx4401 auto sense translator provides bi?directional voltage level shifting to transfer data in multiple supply voltage systems. this device has two supply voltages, v l and v cc , which set the logic levels on the input and output sides of the translator. when used to transfer data from the i/o v l to the i/o v cc ports, input signals refer enced to the v l supply are translated to output signals with a logic level matched to v cc . in a similar manner, the i/o v cc to i/o v l translation shifts input signals with a logic level compatible to v cc to an output signal matched to v l . the nlsx4401 consists of two bi?directional channels that independently determine the direction of the data flow without requiring a directional pin. the one?shot circuits are used to detect the rising or falling input signals. in addition, the one shots decrease the rise and fall time of the output signal for high?to?low and low?to?high transitions. each input/output channel has an internal 10 k pull?up. the magnitude of the pull?up resistors can be reduced by connecting external resistors in parallel to the internal 10 k resistors. input driver requirements the rise (t r ) and fall (t f ) timing parameters of the open drain outputs depend on the magnitude of the pull?up resistors. in addition, the propagation times (t phl / t plh ), skew (t pskew ) and maximum data rate depend on the impedance of the device that is connected to the translator. the timing parameters listed in the data sheet assume that the output impedance of the drivers connected to the translator is less than 50 k . enable input (en) the nlsx4401 has an enable pin (en) that provides tri?state operation at the i/o pins. driving the enable pin to a low logic level minimizes the power consumption of the device and drives the i/o v cc and i/o v l pins to a high impedance state. normal translation operation occurs when the en pin is equal to a logic high signal. the en pin is referenced to the v l supply and has overvoltage tolerant (ovt) protection. power supply guidelines during normal operation, supply voltage v l can be greater than, less than or equal to v cc . the sequencing of the power supplies will not damage the device during the power up operation. for optimal performance, 0.01 f to 0.1 f decoupling capacitors should be used on the v cca and v ccb power supply pins. ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the pcb. the noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the pcb connection traces.
nlsx4401 http://onsemi.com 13 package dimensions udfn6, 1.45x1, 0.5p case 517aq issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip. ??? ??? a b e d bottom view b e 6x 0.10 b 0.05 a c c l 6x note 3 0.10 c pin one reference top view 0.10 c 6x a a1 0.05 c 0.05 c c seating plane side view 1 3 4 6 dim min max millimeters a 0.45 0.55 a1 0.00 0.05 b 0.20 0.30 d 1.45 bsc e 1.00 bsc e 0.50 bsc l 0.30 0.40 l1 ??? 0.15 dimensions: millimeters 0.30 6x 1.24 0.53 pitch *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. 0.50 1 mounting footprint package outline l1 detail a l optional constructions l ??? ??? ??? 0.07 ref 6x a2 detail b detail a on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent? marking.pdf. s cillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data she ets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for e ach customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designe d, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any o ther application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such u nintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this l iterature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 nlsx4401/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative

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